Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are key elements in today's communication systems to achieve the best possible data reception with least possible errors. The basis of turbo coding is to introduce redundancy in the data to be transmitted through a channel by serial/parallel concatenation of convolutional encoders. Using this redundant data the component decoders working iteratively help to recover original data from the received data. This feature makes turbo encoding all the more popular.
FIG. 1 shows a Wideband Code Division Multiple Access (WCDMA) turbo encoder specified in the 3GPP TS 25.212 specification entitled “Multiplexing and channel coding (FDD)”. The WCDMA turbo encoder includes parallel-concatenated recursive systematic convolutional encoders (RSC) with random interleaver in between. The first RSC (3) works on actual input data and the second RSC (4) works on interleaved data provided by the interleaver (2).
The input to the turbo encoder (1) is a 32-bit packet and the output from the turbo encoder (1) is also a 32-bit packet resulting from multiplexed output of both RSCs (3 & 4) by puncturing the non-systematic bit of the second RSC (4). As one stream of input bit results in three output bit streams, the rate of this turbo code is 1/3. After finishing encoding of the input bits both the RSCs (3 & 4) are flushed out such that the state of both RSCs (3 & 4) becomes zero. While flushing the encoder (1), the output tail bits of the first RSC (3) systematic bit followed by parity bit are packed along with the encoded stream. Similarly the output tail bits of the second RSC (4) non-systematic bit followed by parity bit are packed to the output stream.
In a conventional approach, the parity output of the RSC with respect to state, follows a 1st order Markov chain. The conventional approach uses a Look-Up Table (LUT) which gives next state and the output for the given input and present state. The WCDMA turbo encoder table is shown in FIG. 2. The input to the 1st RSC is given bit by bit from the input data and the input to the 2nd RSC is given from the input data by using a pre-calculated interleaver table. The input systematic bit is packed with the output parity bits of both the RSCs in an output register.
As both input and output are 32 bit packed and each encoder parity output depends on the present state, the implementation involves many logical, shift and memory read/write operations. It requires at least one memory read for encoding a single bit to get output or next state information for each RSC and also needs masking of the required bits and shifting to their respective positions and packing with the output register. The above steps are repeated 32 times to process each 32 bit packed input and whenever the output register is full of 32 bits it is stored to the output array.
Further the conventional approach used for implementing turbo coding processes one input bit at a time. This approach consumes many resources and includes many operations. A new approach, which operates on four input bits at a time, has been proposed.